The present disclosure relates to a level converting circuit for level conversion of the voltage level of an input signal, a display device, and electronic apparatus using it.
The level converting circuit (level shift circuit) converts e.g. an input signal whose signal level is the level of the ground potential GND and the level of a first voltage (low supply voltage LVDD) to the signal level of a second voltage (high supply voltage HVDD) higher than the ground potential GND and the first voltage.
Because the level converting circuit uses the high supply voltage HVDD, a high-breakdown-voltage transistor needs to be used. The existing level converting circuits (level shifters) are all configured by using the high-breakdown-voltage transistor.
However, in recent years, along with a decrease in the breakdown voltage, it becomes difficult to supply a sufficiently-high overdrive voltage ov to the gate of a high-breakdown-voltage NMOS transistor and thus the level converting circuit is obliged to have an increased area for capability enhancement.
In such circumstances, there have been proposed techniques of supplying a bias higher than the low supply voltage LVDD to the gate of a high-breakdown-voltage NMOS transistor and carrying out level conversion with use of a low-voltage power supply for speed enhancement, area reduction, and stable operation (refer to e.g. Japanese Patent Laid-open No. 2006-19815, Japanese Patent Laid-open No. 2005-311712, and Japanese Patent Laid-open No. 2003-101405 (hereinafter, Patent Documents 1 to 3, respectively)).
FIG. 1 is a circuit diagram showing the configuration of a level converting circuit disclosed in Patent Document 1.
A level converting circuit 1 of FIG. 1 has n-type field effect transistors (NMOS transistors) NT1 to NT7 and p-type field effect transistors (PMOS transistors) PT1 to PT3.
The NMOS transistors NT1, NT2, and NT5 and the PMOS transistors PT1 to PT3 are formed of high-breakdown-voltage MOS transistors. The NMOS transistors NT3, NT4, NT6, and NT7 are formed of low-breakdown-voltage MOS transistors.
The level converting circuit 1 has an input terminal T1 to which an input signal of 0 to 5 V is applied, a low-voltage (5 V) power supply terminal T2, a ground terminal T3, a high-voltage power supply terminal T4, inverters IV1 and IV2 that operate by a low-voltage power supply, an inverter IV3 for a high-voltage power supply, and an output terminal T5.
In the level converting circuit 1, the gate voltage of the PMOS transistor PT3 forming a bias circuit 2 is so set that its source-drain current is kept at 3 μA. The transistor characteristics of the PMOS transistor PT3 forming the bias circuit 2 and the NMOS transistor NT5 are set identical to those of the PMOS transistor PT1 and the NMOS transistor NT1. The circuit of the transistor NT5 and the circuit of the transistor NT1 configure a current mirror circuit.
Due to this feature, the source voltage of the NMOS transistor NT1 is the same as that of the NMOS transistor NT5 and kept at 5 V. This applies also to the circuit of the PMOS transistor PT2 and the NMOS transistor NT2.
The drain voltage of the NMOS transistors NT3 and NT4 is equal to or lower than the voltage of the low-voltage power supply terminal T2. As a result, a large current is permitted to flow as the source-drain current of the NMOS transistors NT3 and NT4 even when the voltage of the low-voltage power supply terminal T2 is lowered, and driving by a lower input signal is enabled.
FIG. 2 is a circuit diagram showing the configuration of a level converting circuit disclosed in Patent Document 2.
For easy understanding, the same constituent part in a level converting circuit 1A of FIG. 2 as that in FIG. 1 is represented by the same symbol.
In the level converting circuit 1A of FIG. 2, the current flowing in a bias circuit 2A is controlled by a control signal EN obtained by inverting a control signal ENX from the external by an inverter IV6.
FIG. 3 is a circuit diagram showing the configuration of a level converting circuit disclosed in Patent Document 3.
For easy understanding, the same constituent part in a level converting circuit 1B of FIG. 3 as that in FIG. 1 and FIG. 2 is represented by the same symbol.
In the level converting circuit 1B of FIG. 3, a bias circuit (intermediate voltage generating circuit) 2B is formed as a source follower circuit and configured with a PMOS transistor PT8 and a resistor R2.